Extracting of Substrate Network Resistances in RFCMOS

In this paper substrate network resistances are analyzed and extracted for multi-finger MOS transistors used in RF applications. The commonly used model for MOS transistors in RF applications mainly consists of a substrate resistance network having three resistors. A typical horse-shoe CMOS transistor laid out and all substrate resistances are extracted from I-V characteristics. Device and process simulation results for 0.25μm CMOS technology show that the horse-shoe structure decreases the parasitic substrate resistance by 27%. Additionally, we show that the results obtained from traditional approximation method deviated about 31% from the exact results. Furthermore, with proposed method, the substrate resistance values can be exactly extracted.